Cell-based clock recovery device

ABSTRACT

A clock recovery unit provides a clock recovery function in the receiving entity of a system to implement adaptation of constant bit-rate (CBR) services over an asynchronous transfer mode (ATM) or ATM-like network. Incoming cells are periodically sampled for buffer fill level L i . The maximum fill level of undelayed cells Lx j  is extracted from successive series of a predetermined whole number M of buffer-fill samples L i . A frequency adjustment logic unit provides at its output a bit stream at a given clock frequency f j . The frequency adjustment logic unit makes incremental adjustments to the clock frequency f j  tending to cause the steady state mean of the fill level Lx j , or its derivative, to move toward zero.

FIELD OF THE INVENTION

This invention relates to digital transmission systems, and moreparticularly to a cell-based clock recovery (CBCR) device for providinga clock recovery function in the receiving entity of a system toimplement adaptation of constant bit-rate (CBR) services over anasynchronous transfer mode (ATM) or ATM-like network.

DESCRIPTION OF PRIOR ART

Asynchronous Transfer Mode (ATM)) is a high-speed digital communicationsprotocol for which the basic functional unit is a fixed-length 424-bit(53-byte) cell. Five bytes of each cell are allocated for routing andcontrol, and the remaining 48 bytes are used for data transport. Onentry to an ATM-based network, information is loaded into cells inaccordance with standardized formatting protocols called adaptationprotocols. Once the cell has being filled, it is transported through thenetwork as soon as possible. Buffers are used throughout ATM-basednetworks to deal with congestion, i.e., cases where more than one cellis ready for transport over a given communications link.

As suggested by the name, constant bit rate (CBR) services transmit databits at a nominally constant rate. More specifically, transmittingentities for CBR services use a reference clock to time the delivery ofdata bits. Receiving entities must access the same clock, eitherdirectly or indirectly, to retrieve the data.

Reference clocks used in CBR services must operate within standardizedspecifications for mean operating frequency, maximum jitter and maximumwander. Jitter and wander are constraints on high-frequency variabilityand low-frequency variability about the mean operating frequency,respectively. Jitter and wander are generally measured in terms of theoffset of clock pulses from where they would be if the clock wereconsistently operating at precisely its mean operating frequency. Jitteris short-term deviation in the pulse center-points from where they wouldbe if the clock was fixed at its mean frequency. Wander is theequivalent long term variation. Jitter is measured in the order ofHertz, whereas wander is measured in the order of hours or days.

The following specifications, drawn from the ANSI specification for T1service, provide an example of requirements for CBR clocks. Here a UI isa unit interval or clock period, which for T1 is 648 ns:

The mean operating frequency must be 1.544±50 Hz.

Jitter in the frequency band between 10 HZ and 40 KHz must be less than0.5 UI peak-to-peak, and jitter in the frequency band between 8 Khz and40 Khz must be less than 0.07 UI peak-to-peak.

Wander must be less than 5 UI peak-to-peak over any 15-minute period,and must be less than 28 UI peak-to-peak over any 24-hour period.

Clock recovery is a process by which entities within a communicationsnetwork gain access to a reference clock when needed. There are twobasic approaches to clock recovery. The first approach entails applyingrelatively simple techniques to a clock signal that is separatelytransmitted to the receiving entity. The other approach is to extractthe clock from an analysis of the periodicity of the received datasignal. While the second approach is generally more complex to implementand more prone to error, it obviates the need for transmission of aseparate clock signal. Cell-based clock recovery is an example of thesecond approach.

When CBR services are transported over an ATM network, a recommendedbasis for controlling the output clock in the receiver is to monitor thebuffer fill level CCITT, B-ISDN--ATM Adaptation Layer for Constant BitRate Services: Functionality and Specification, Draft T1S1/92-570, Nov.13, 1992!. If the receiver's output clock is slower than the sender'sinput clock, then the buffer fill-level will tend to increase with time.Conversely, if the receiver's output clock is faster than the sender'sinput clock, then the buffer fill-level will tend to decrease with time.The output clock can thus be adjusted based on trends in the bufferfill-level. In this arrangement, it is not necessary for both the senderand the receiver to have access to a common network clock. The approachcan thus be used in more situations than the alternative recommendedclock recovery method, i.e., the synchronous residual time stamp (SRTS)method. Such a method is described, for example, in PCT application no.PCT/EP88/00178 (WO 88/07297).

Large coincident variations in the buffer fill-level can be expected.Firstly, the buffer fill-level plotted as a function of time looks likea saw-tooth because data are inserted into the buffer in cell-sized(53-byte) blocks but are drained from the buffer one bit at a time.Secondly, variation in the observed buffer fill level can be introducedby the sequencing and relative prioritization of tasks performed withinthe service adaptation system. For example, such processing jitter inthe transmitting entity can cause variation in the time spacing betweentransmitted cells which will manifest itself as buffer fill-levelvariation in the receiving entity. Finally, time-varying queuing delayswill occur at points of congestion within the network. As withprocessing jitter, such time-varying queuing delays manifest themselvesas buffer fill-level variation.

Of the three sources of coincident fill-level variation mentioned above,the most problematic is queuing delays within the network. Processingjitter is under the control of the system designer and can be reduced toa manageable level by proper design. The saw-tooth effects can beminimized by roughly synchronizing the sampling of the buffer fill-levelwith the arrival of ATM cells.

The Newbridge Mainstreet™ 36150 switch provides insight into themagnitude of fill-level variation due to queuing delays. The ATM cellspass through three switching stages, each of which has a 16-cell queue.The worst case scenario introduces a queuing delay of 48 cells. Giventhat 2.74 μs (i.e. 53 bytes at 155 Mbits/sec) are needed to transmit anATM cell, the queuing delay through a single switch can be up to 132 μs.Allowing for processing jitter and the possibility of encountering anumber of ATM switches, queuing delays can be expected to vary betweenzero and, say, 1000 μs. For T1 service adaptation this translates to abuffer-fill-level variation in the order of +/-800 bits.

Other queues in the network can be much longer than those of theMainstreet™ 36150 switch. For example, the Newbridge T3 line interfacecard has a queue for up to about 3 ms of data. A delay variation of upto 3 ms may be encountered if ATM cells for T1 service are passedthrough the T3 card.

An approximate analysis for satisfying the T1 jitter requirements is asfollows: if the clock estimate is updated at a rate of about 20 Hz, themaximum allowable frequency mismatch is about 10 Hz to satisfy the 0.5UI jitter upper limit. This corresponds to a clock period that isaccurate to within about 4 ps. Larger errors in the clock period can inprinciple be tolerated if the frequency of the clock update isincreased. However, this does not simplify the task because less newdata is available from which to obtain each frequency estimate.

The magnitude of the task to be performed is quite striking. Therequirement is to derive an unbiased estimate of the T1 transmitter'sclock period to an accuracy of a few picoseconds by analyzing, ineffect, the periodicity of ATM cell arrival. However, cell arrivaljitter of the order of +/-500 μs or more can be expected. It followsthat the jitter variance must be reduced by a factor of in the order of10¹².

Clock wander is important to control in CBR services and is asignificant problem within conventional cell-based cock recoverysystems. Wander is important because buffers within some CBR networksare sized based on the wander requirements, and may in certaincircumstances overflow if these requirements are not met. The problemwith wander for conventional CBCR arises because the clock is, ineffect, set based on low-pass filtered samples of the buffer fill level.Unfortunately, no matter how low one sets the roll-off frequency of thelow-pass filter, there is always in principle a lower-frequencycomponent that can get through the filter. Such components appear asclock wander. Because the size of such lower-frequency componentsdepends on a variety of uncontrolled factors, it is difficult to specifylimits of wander in CBCR systems and to verify conformance withstandards for wander.

An object of the present invention is to address the aforementionedproblems of the prior art.

SUMMARY OF THE INVENTION

According to the present invention there is provided a clock recoveryunit for providing a clock recovery function in the receiving entity ofa system to implement adaptation of constant bit-rate (CBR) servicesover an asynchronous transfer mode (ATM) or ATM-like network, comprisinga buffer for receiving incoming cells, means for periodically samplingthe buffer fill level L_(i), means for obtaining an estimate Lx_(j) ofthe buffer fill level on arrival of substantially undelayed cells from aseries of buffer fill-level samples L_(i), and a frequency adjustmentlogic unit providing at its output a control signal at a given clockfrequency f_(j), said frequency adjustment logic unit making incrementaladjustments to said clock frequency f_(j) to cause the steady state meanof said estimate Lx_(j) of the buffer fill level on arrival of undelayedcells, or a derivative thereof, to move toward a predefined optimaloperating point L_(opt).

In one embodiment, the estimate Lx_(j) is derived from blocks offill-level samples, each block containing a predetermined number M ofsamples. However, the number of samples can change from block to block.

The control signal produced by the invention may be in the form of a bitstream, sine wave or other representation of the frequency of thederived clock.

The sampling of the buffer fill-level should normally be carried out inapproximate synchronization with the arrival of cells to minimize theeffects of the saw-tooth shape of the fill level of the buffer for thereasons specified.

One estimator of the buffer fill level on arrival of undelayed cells isthe maximum of a block of fill-level samples. As indicated earlier theactual buffer fill level is in the form of a saw-tooth waveform becausethe cells arrive as a single block of 424 bits are then output one bitat a time at a constant rate. If the arriving cells are delayed, thefill level will tend to fall because more bits will be output before newcells arrive. The maximum fill level will occur when the cells arrive ontime. The estimated maximum fill level is thus representative of thefill level for undelayed cells.

While the interfering traffic in the network may frequently createpoints of substantial congestion, it should also be relatively commonfor cells to pass through the network without substantial delay. Thus,the minimum of the cell delivery delays for a series of ATM cells shouldbe relatively unaffected by the interfering traffic. It follows that themaximum buffer fill-level will also be relatively unaffected. Even ifthis is not completely true, it is reasonable to say that phenomenawhich increase the mean cell transmission delay will also increase thevariance of the cell transmission delay, so the minimum delay willundergo a smaller change than the mean delay or the maximum delay.

The buffer fill level on arrival of undelayed cells can also beestimated from the weighted sum of two or more statistics drawn from ablock of fill-level samples. For example, the mean fill level and/or theminimum fill level could be used in combination with the maximum filllevel to obtain a composite estimate which, under certain conditions,leads to less wander than when the maximum fill-level is used inisolation.

When compared with the traditional approach of using the mean bufferfill level, the advantage of using the maximum buffer fill level orother estimate of the buffer fill level on arrival of undelayed cells,is particularly pronounced when a single bursty source of interferingATM traffic periodically swamps the capacity of some point of congestionwithin the network. In this case the mean buffer fill level observed bythe receiving entity will be severely affected by the interferingtraffic, but the maximum buffer fill level or other estimate of thebuffer fill level on arrival of undelayed cells will be relativelyunaffected.

The invention also provides a method of providing a clock recoveryfunction in the receiving entity of a system to implement adaptation ofconstant bit-rate (CBR) services over an asynchronous transfer mode(ATM) or ATM-like network, characterized in that it comprises the stepsof receiving incoming cells in a buffer; periodically sampling thebuffer fill level L_(i) ; estimating Lx_(j) of the buffer fill level onarrival of substantially undelayed cells from a series of bufferfill-level samples L_(i) ; outputting a control signal at a given clockfrequency f_(j) ; and making incremental adjustments to said clockfrequency f_(j) to cause the steady state mean of the estimate Lx_(j) ofthe buffer fill level on arrival of undelayed cells, or a derivativethereof, to move toward a predetermined optimal operating value.

The invention has been described with reference to an ATM network, butit is applicable to any similar type of packet-switched network havingcells of data that are propagated through the network. The cells neednot necessarily be of fixed length, and the invention is equallyapplicable to a packet-switched network employing blocks of data ofvariable size.

BRIEF DESCRIPTION OF THE DRAWING

The invention will now be described in more detail, by way of exampleonly, with reference to the accompanying drawings, in which:

FIG. 1 is a general block diagram of a cell-based clock recovery unit inaccordance with the invention;

FIG. 2 is a general block diagram of one embodiment of a clock recoveryunit in accordance with the invention;

FIG. 3 illustrates a mathematical model of the clock recovery methodemployed in the invention; and

FIG. 4 shows the variation in buffer bill level with time.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, incoming 53-byte ATM cells 21 are input tobuffer 1 as they arrive from the network. The buffer outputs bits at aconstant bit rate. As a result the fill level of the buffer 1 as afunction of time can be represented by a saw-tooth waveform as shown inFIG. 4, which shows the fill level for undelayed cells in solid outline.The rising edge occurs when a cell arrives. If the cells are delayed themaximum fill level falls as shown in broken outline because more bitsare output before the arrival of the next cell.

Referring again to FIG. 1, the fill-level L_(i) of the buffer 1 ismonitored by buffer fill-level detector 2. The samples of the bufferfill-level L_(i) are obtained by periodic sampling of the bufferfill-level in approximate synchronization with the arrival of ATM cellsto minimize the effects of the sawtooth shape of the fill levelwaveform.

The samples L_(i) are passed to block 3, which is an estimator of bufferfill level for undelayed cells. This extracts its estimates from asequential number M of buffer fill-level samples L_(i), producingLx_(j), which is only updated after M new samples of L_(i) have beenscanned. That is subscript j increments M times slower than subscript i.M is a predetermined configuration parameter for the invention.

The fill level estimator can be a local maximum estimator, for example,or alternatively a unit taking the weighted summation of the mean filllevel, the maximum fill level, or other statistics from a block offill-level samples.

The output of block 3 is then fed to subtractor 4, which subtracts apre-determined steady state optimum buffer fill level L_(opt) fromLx_(j), and the result is passed to the frequency adjustment logic block6 along with an estimate of the derivative of Lx_(j) produced bydifferentiator 5.

The choice of L_(opt) is a choice between starvation avoidance and delayminimization. Larger values of L_(opt) are needed to avoid starvation(buffer underflow) when cells are severely delayed during transmission.Small values of L_(opt) are preferred to keep the mean delay within thenetwork low. The parameter L_(opt) provides a direct means of obtaininga balance between these two factors.

The frequency adjustment logic block 6 generates a signal representing aclock frequency f_(j). Frequency adjustment logic block 6 then makessmall incremental adjustments to the clock frequency f_(j) such that thesteady-state mean of one or both of its inputs tends toward zero.

FIG. 2 provides a detailed illustration of a preferred embodiment of theinvention. L_(i) represents sample i of the buffer fill level, Lmax_(j)sample j of the recovered clock frequency, L_(opt) the optimumsteady-state maximum buffer fill level, is the index for the samples ofbuffer fill level, and j is the index for samples of the clock frequencyand the maximum buffer fill level.

The Divide-by-M block 9, Maximum Extractor Block 10 and the MaximumSample-and-Reset block 11 correspond to the block 3 of FIG. 1 since theyprovide an estimate of the fill level of undelayed samples. The block 10outputs a signal representing the maximum of the fill level samplesL_(i) received from the fill level detector 2. Block 11 outputs themaximum Lmax_(j) for each M samples and at the same time resets themaximum extractor 10. The result is an output signal Lmax_(j) thatrepresents the buffer fill level for undelayed samples.

An optimization signal L_(opt), which is an optimization parameter forthe system that depends on the operating conditions, is subtracted fromLmax_(j) in summer 4. The output of summer 4 is input to the J sampledelay block 12 and summer 13, which together correspond to thedifferentiator block 5 of FIG. 1.

Multipliers 14, 15 and summer 16 correspond to the Frequency AdjustmentLogic block 6 of FIG. 1.

The embodiment shown in FIG. 2 implements the recursion relationship:

    f.sub.i =f.sub.j-1 +α×HDLIM.sub.α (Lmax.sub.j -Lmax.sub.j-J)+β×(HDLIM.sub.β (Lmax.sub.j -Lopt)

where

f_(j) =output clock frequency (Hz)

Lmax_(j) =the maximum of M successive samples of the buffer fill level(bits)

M=the length of the block from which each Lmax_(j) is extracted(samples)

Lopt=the optimal buffer fill level (bits)

α=first-order adaptation factor (Hz/bit)

β=second-order adaptation factor (Hz/bit)

J=the block separation

HDLim.sub.α =hard limit with threshold THR.sub.α

HDLim.sub.β =hard limit with threshold THR.sub.β

In the absence of coincident sources of variation, the buffer fill-levelchanges in direct proportion to the difference between the transmittingentity's clock and the receiving entity's clock. Thus, α serves to adaptf_(j) toward the input clock frequency. The other factor β performs thesecondary function of moving the buffer fill-level toward thepreselected "optimal" value L_(opt). Without β, the unit will come torest at an arbitrary fill level which may be too low to avoid starvation(buffer underflow) or too high to avoid buffer overflow. Furthermore,without β the end-to-end transmission delay of the adaptation system isnot controlled.

The hard limiting operator HDLIM.sub.α, serves to reduce the impact ofoccasional large spikes in the driving function that can arise when thenetwork delay suddenly changes. The invention relies on what amounts tothe derivative of the buffer fill level. A step in the fill level thustranslates to a large spike in the clock adjustment. Such steps in thefill level can result if the network delay properties suddenly change.

The hard limiting operator HDLim.sub.β serves to control the excursionthe output frequency when a large change in the buffer fill level isneeded. Such large changes can occur if the network delay suddenlychanges or if the target fill level (Lopt) is altered.

The following is a general analytical analysis of the embodiment shownin FIG. 2, which will explain the underlying principle of the inventionin more detail.

A Z-Transform representation of a generalized version of the recursionrelationship presented above is:

    F(z)=D(z) (L(z)+N(z))

where

F (z)=Z transform of the output frequency

D (z)=Z transform of the adaptation filter

L (z)=Z transform of the maximum buffer fill level

N (z)=Z transform of the error in estimates of L(z)

The maximum buffer fill level satisfies the following relation in theabsence of jitter provided that the frequency parameters remainapproximately constant over the interval of analysis:

    Lmax.sub.j =Lmax.sub.j-1 +T (fin.sub.j-1 -f.sub.j-1)

where

fin_(i-1) =the frequency of the CBR source clock

T=the time separation of fill-level estimates Lmax_(j) and L_(j-1)

By deriving the Z transform of Lmax_(j) and substituting it into theinitial expression for F(z) we obtain:

    F(z)=H(z) Fin(z)+((H(z) (z-1))/T) N(z)

where

    H(z)=D(z)T/(z-1+D(z)T)

The above expressions are represented by a digital phase-locked loop(DPLL)-like structure as shown in FIG. 3. Since the element 1/(z-1) isan integrator, the buffer fill-level is the integral of the frequencydifference, and thus is effectively the phase error of the loop. Thelinearized baseband model of a classical DPLL can be derived, forexample as described in "A survey of Digital Phase-Locked Loops,"Proceedings of the IEEE, April 1981, pp 410-431, by backing theintegrator 1/(z-1) out of the loop through the summer. An equivalentcircuit for FIG. 3 is obtained by removing the 1/(z-1) block from itscurrent position in the loop and applying it instead to both f_(j) andfin_(j) prior to their summation. The main remaining difference betweenthis result and that described in the above article is in scaling of thenoise and the loop filter. Thus, much of the standard analyses commonlyperformed for classical DPLLs are applicable.

The analytical representation presented above has a loop filter of theform:

    D(z)=(α(1-z.sup.-J)+β)/(1-z.sup.-1)

from which is obtained: ##EQU1##

For T1 service adaptation the time interval T is:

    T≈BM/fin

where

B=number of data bits per cell (376 for ATM)

M=number of cells per block

fin=nominal source clock frequency (1.544 Mhz for T1)

The stability of the above-described system will now be considered.Through repeated application of the Jury stability test to H(z) when theloop filter has the form D (z)=(α(1-z^(-J))+β)/1-z⁻¹, it was found thatthe loop is stable if the following conditions are satisfied:

    0<αT<2.sup.2-J -βT/2

    0<βT<2.sup.3-J -2αT

The loop will exhibit a highly oscillatory behavior as it nears thelimits of stability, and extra delay in the loop can push it towardsinstability. It is thus important to operate well inside the stabilitylimits.

Extra delays in the loop lead to an increased tendency for oscillatorybehavior, and can make an otherwise stable loop unstable. For example,if J=1 and if there is an extra one-sample delay in the loop (i.e., adelay of T seconds), the Jury stability test produces the followinglimits for obtaining stability: ##EQU2## when J=I and delay=T

One can see that the upper limits are substantially less than they wouldbe without the extra delay.

A properly-designed loop must provide more than just stability: itshould have few if any oscillations when presented with sudden inputchanges. For the present application, such oscillations occur when β istoo large relative to α. In the special case of J=1, the transferfunction becomes: ##EQU3## where ##EQU4##

From an inspection of the denominator of H(z)|_(J=1) it is apparent thatthe loop response is critically damped when b=0. This means that thefollowing inequality should be applied to avoid oscillatory behavior:##EQU5## when J=1

Now, with β=0 the convergence properties of the loop are quiteconsistent when α×J is constant. The choice of J also has little effecton the influence of β on the loop dynamics. Therefore, the followingexpression can be used to obtain a nearly-critically-damped loop forarbitrary J: ##EQU6##

It should be emphasized that this expression is only an approximation.For example, when J>1 it is possible for α alone to introduceoscillations. Additional loop delays can also introduce oscillations.Thus, it is prudent to choose βT such that the loop is somewhatoverdamped.

A simple measure of the convergence rate of the loop can be derived fromthe proportion of the estimated frequency difference that is correctedin a single step. While this ignores interaction between α and β andprovides only a tangential approximation for the convergence, it hasbeen found to be consistently representative for all practical parameterselections. Now, we know that

    Lmax.sub.j -Lmax.sub.j-J =TJ(fin.sub.j -f.sub.j)

From this it appears that the α that would correct a frequency mismatchin a single step is:

    α.sub.1 =1/TJ

Thus, the proportion of frequency correction in a single step is α/α₁,and rate of frequency change per unit time is:

    RATE=α/α.sub.1 T=αJ

The interpretation of RATE is that a step discontinuity in the inputfrequency will be resolved by the loop in about 1/RATE seconds. Theactual rate tends to be slower. For example, if one inspects the actualresponse of a critically-damped loop to a frequency step, one finds thatthe time it takes for the output frequency to match the input (i.e., thefirst zero crossing in the frequency error plot after the stepdiscontinuity), is about 1.8/RATE. It is interesting to note that theconvergence rate is not affected by the block size (M) or, implicitly,the update period T.

There is a direct nonlinear relationship between RATE and the -3 dBrolloff point of the closed-loop frequency response of the loop(f_(3dB)). If RATE is well below its maximum, i.e., if α<<α₁, thenf_(3dB) ≈RATE/6 Hz. The divisor is larger for higher values of RATE. Thedivisor is between 5.5 and 6 for the configurations recommended in thisdocument.

An approximate analysis of worst-case buffer fill-level excursion duringfrequency convergence is to temporarily set β to zero. This isreasonably accurate because the approximate behavior of a criticallydamped second-order loop when presented with a step discontinuity in theinput frequency is to first resolve the frequency mismatch at the ratedetermined by α and J, and then slowly bring back the buffer fill-levelto Lopt at a rate determined by β. Now, since the proportion offrequency correction on each iteration is α/α₁, the change in fill levelover N iterations is:

    ΔL=Δf T (1+(1-α/α.sub.1)+(1-α/α.sub.1).sup.2 +(1-α/α.sub.1).sup.N-1

where

ΔL=fill-level change (bits)

Δf=size of the frequency step (Hz)

Taking the limit as N goes to infinity one obtains:

    ΔL=(Δf T α.sub.1)/α=Δf/RATE

Simulations indicate that this expression overestimates the fill-levelexcursion by a factor of about 1.3 for a critically-damped loop. Theoverestimate is less for over-damped loops.

An analysis will be made of the frequency disturbance due to fill leveladjustment. This is an analysis of the peak frequency disturbance whenthe loop acts to resolve a deviation of the buffer fill-level from itsprespecified "optimal" value (L_(opt)). Such a response will result ifthe Lopt parameter is adjusted during processing or if clock recoverydevice is activated when the buffer fill-level deviates significantlyfrom L_(opt). For the present approximate analysis, Lmax_(i) -L_(opt) inthe adaptation equation are replaced with the constant ΔL_(opt), thehard-limits are disabled, and the resulting steady-state frequencydifference Δf is computed. If ΔL_(opt) is the initial size of thefill-level deviation, then Δf will be a rough estimate of the peakfrequency disturbance. The modified adaptation equation comes to restwhen α(L_(i) -L_(i-J))=βL_(opt). Since Lmax_(i) -Lmax_(i-J)=TJ(fin-fout), it follows that the steady-state frequency difference is:##EQU7##

This expression overestimates the peak frequency disturbance because itignores the fill-level adaptation that occurs before we reach the peak.Simulations indicate that it overestimates by a factor of about 1.3 fora critically-damped loop. The overestimate is less for over-dampedloops.

It is also necessary to consider the hard limiting effects of THR.sub.βand THR.sub.α. The hard-limiting threshold THR.sub.β is present tocontrol the range of frequency excursion when the fill-level deviatesfrom its prespecified "optimal" value. Using the same logic as waspresented in the preceding section, it can be shown that a sustainedfill-level deviation which exceeds THR.sub.α will result in thefollowing frequency offset: ##EQU8##

The hard-limiting threshold THR.sub.α limits the influence of suddenlarge changes in the fill level due possibly to extraordinary amounts oferror in the fill level estimates. This is intended for use as a meansof rejecting widely deviant samples. One should avoid bringing it tooclose to the normal range of variation because it reduces α and may thuspush the loop into oscillation or instability when β is nonzero.

Formal analysis of the noise output of the loop requires a rathertedious contour integration and is not needed for gathering a generalinsight into its behaviour. First, let β=0 for the purpose of thisanalysis, because it is always much less than α for practical loops.This leads to the following approximation for the loop filter:

    f.sub.j -f.sub.j-1 ≈α(Lmax.sub.j -Lmax.sub.j-J)

If we run through the recursion we find that each output sample (f_(j))is the sum of J successive input samples Lmax_(j). If it is assumed thatthe input noise is uncorrelated, then

    σ.sup.2.sub.f =α.sup.2 Jσ.sup.2.sub.L

where

σ² _(L) =variance of the maximum buffer fill level (bits²)

σ² _(f) =variance of the output frequency (Hz²)

For the purpose of this analysis it is assumed that σ² _(L) is the sameas the variance of the average buffer fill level obtained from a blockof M fill-level samples. Thus, ##EQU9## where σ² _(L) =variance of theATM cell arrival times (sec²)

This leads to the following expression for the frequency jitter (in Hz²)##EQU10##

Finally it is common to specify jitter in terms of unit intervals ratherthan frequency, where a unit interval is a period of the T1 clock (648ns).

The following formula, with the dimension UI² provides a roughcomparison with such specifications:

    σ.sup.2.sub.UI =σ.sup.2.sub.J T.sup.2 ≈RATE×β.sup.2 Mασ.sup.2.sub.δ

The choices of M and J are affected by factors other than noisereduction. For example, each increment of J increases the order of theloop filter, thereby making it more difficult to analyze and tighteningthe stability constraints. A small M implies a small T which leads to apotentially larger impact of the delay on the loop performance andstability.

The preferred settings for T1 clock adaptation are summarized in theTable below. For both modes the loop is updated with a frequency ofabout 20 Hz, i.e. T=200/4106=0.0487 secs. The loop parameters are wellwithin the stability range bounds. The fast adaptation configurationproduces a system having a -3 dB rolloff of about 0.1 Hz. It produces amaximum fill level excursion of ΔL<200 bits in response to a 100 Hzfrequency step, and a maximum disturbance of Δf_(ss) <30 Hz in responseto a large fill-level adjustment. The slow adaptation configurationproduces a system having a -3 dB rolloff of about 0.03 Hz. It produces amaximum fill level excursion of ΔL<500 bits in response to a 100 Hzfrequency step, and a maximum disturbance of Δf_(ss) <11 Hz in responseto a large fill-level adjustment. It is finally both configurable andsufficiently overdamped to provide a maximum low frequency amplificationof less than 0.5 dB.

                  TABLE                                                           ______________________________________                                        Parameter     Adaptation Fast                                                                          Mode Slow                                            ______________________________________                                        RATE          1/2        1/5                                                  α       0.0625     0.025                                                β        α/70 α/200                                          J             8          8                                                    M             200        200                                                  THR.sub.α                                                                             256        256                                                  THR.sub.β                                                                              800        800                                                  ______________________________________                                    

The described embodiments of the invention are capable of providing CBRservice adaptation in an ATM network.

I claim:
 1. A clock recovery unit for providing a clock recoveryfunction in the receiving entity of a system to implement adaptation ofconstant bit-rate (CBR) services over an asynchronous transfer mode(ATM) or ATM-like network, comprising a buffer for receiving incomingcells; a sampling unit for periodically sampling the buffer fill levelL_(i) ; an estimation unit for obtaining an estimate Lx_(j) of thebuffer fill level on arrival of substantially undelayed cells from aseries of buffer fill-level samples L_(i) ; and a frequency adjustmentlogic unit providing at its output a control signal at a given clockfrequency f_(j), said frequency adjustment logic unit making incrementaladjustments to said clock frequency f_(j) to cause the steady state meanof said estimate Lx_(j) of the buffer fill level on arrival of undelayedcells, or a derivative thereof, to move toward a predefined optimaloperating point.
 2. A clock recovery unit as claimed in claim 1, whereinsaid estimation unit comprises means for extracting the maximum filllevel of said predetermined number of samples.
 3. A clock recovery unitas claimed in claim 1, wherein said estimation unit comprises means forderiving a composite estimate from a mean fill level of said buffer incombination with a maximum fill level of said buffer.
 4. A clockrecovery unit as claimed in claim 1, wherein said estimation unitcomprises means for deriving a composite estimate from a minimum filllevel of said buffer in combination with a maximum fill level of saidbuffer.
 5. A clock recovery unit as claimed in claim 1, wherein saidsampling unit samples the buffer fill-level in approximatesynchronization with the arrival of ATM cells.
 6. A clock recovery unitas claimed in claim 1, further comprising a subtractor for subtracting apredetermined optimal value L_(opt) from the estimate of the bufferfill-level Lx_(j) to produce a difference value, a differentiator forderiving the derivative of said estimate of the buffer fill-levelLx_(j), said difference value and the derivative of said estimate of thebuffer fill-level Lx_(j) being applied as first and second inputs tosaid frequency adjustment logic unit which is adapted to incrementallyadjust said clock frequency fj to cause one or both of the inputsthereof to move toward said predetermined optimal value.
 7. A clockrecovery unit as claimed in claim 2, wherein said estimation unitextracts the maximum fill level Lmax_(j) and includes a divider fordividing the clock rate of the samples by a number M and aMaximum-Sample-and-Reset unit for producing at its output a signalrepresenting Lmax_(j).
 8. A clock recovery unit as claimed in claim 7,wherein said differentiator is provided by a J sample delay circuit anda subtractor.
 9. A clock recovery unit as claimed in claim 8, whereinsaid frequency adjustment logic unit includes a pair of multipliers eachhaving respective first inputs receiving a value dependent on themaximum fill-level Lmax_(j) and the derivative thereof, and secondinputs receiving predefined configuration parameters α and β.
 10. Aclock recovery unit as claimed in claim 9, wherein said frequencyadjustment logic unit comprises hard limit units connected to respectivemultipliers, and a summer for summing the outputs of said multipliers toproduce said control signal, said summer having its output looped backto a third summation input.
 11. A clock recovery unit as claimed inclaim 10, further comprising a one sample delay unit between the outputof said summer and said third input thereof.
 12. A clock recovery unitas claimed in claim 11, wherein α is about 0.0625 and β is about 0.0009in a fast adaptation mode.
 13. A clock recovery unit as claimed in claim12, wherein α is about 0.025 and β is about 0.0001 in a slow adaptationmode.
 14. A clock recovery unit as claimed in claim 1, wherein saidmeans for obtaining an estimate of the buffer fill level obtains saidestimate from successive series of samples, each having a number M ofsamples.
 15. A clock recovery unit as claimed in claim 14, wherein M isconstant from one series of samples to the next.
 16. A clock recoveryunit as claimed in claim 14, wherein M varies from one series of samplesto the next.
 17. A method of providing a clock recovery function in thereceiving entity of a system to implement adaptation of constantbit-rate (CBR) services over an asynchronous transfer mode (ATM) orATM-like network, comprising the steps of receiving incoming cells in abuffer; periodically sampling the buffer fill level L_(i) ; estimatingthe buffer fill level on arrival of substantially undelayed cells Lx_(j)from a series of buffer fill-level samples L_(i) ; outputting a controlsignal at a given clock frequency f_(j) ; and making incrementaladjustments to said clock frequency f_(j) to cause the steady state meanof the estimate Lx_(j) of the buffer fill level on arrival of undelayedcells, or a derivative thereof, to move toward a predetermined optimalvalue.
 18. A method as claimed in claim 17, wherein said estimate Lx_(j)is derived from a maximum fill level of said buffer.
 19. A method asclaimed in claim 17, wherein said estimate is obtained from successiveseries of M samples, wherein M is the number of samples in a saidseries.
 20. A method as claimed in claim 19, wherein M is constant fromone series of samples to the next.
 21. A method as claimed in claim 19,wherein M varies from one series of samples to the next.